1. Field of the Invention
The present invention relates, in general, to semiconductor memory devices and, more particularly, to a semiconductor memory device, which has a layout including sub-array regions, and bit line sense amplifier regions and word line driver regions that are adjacent to the sub-array regions.
2. Description of the Related Art
A semiconductor memory device includes a memory array, in which memory cells, that is, storage devices for storing data, are arranged in a matrix array of rows and columns. In this case, word lines WL are arranged in rows, and bit lines BL are arranged in columns. The memory cells MC are arranged at the intersections of word lines WL and bit lines BL.
As shown in FIG. 1, a memory array is divided into a plurality of sub-arrays S_ARR. Sense amplifier regions BK_SA are disposed between two sub-arrays S_ARR that are adjacent to each other in the direction of bit lines BL. Further, word line driver regions BK_SWD are disposed between two sub-arrays S_ARR that are adjacent to each other in the direction of word lines WL. Further, junction regions JNC are disposed at the intersections of the sense amplifier regions BK_SA and the word line driver regions BK_SWD.
Meanwhile, in the semiconductor memory device, high integration is one among a number of very significant technical concerns. In order to more highly integrate a semiconductor memory device, technology for reducing the area of the sense amplifier regions BK_SA and the word line driver regions BK_SWD and efficiently arranging the sense amplifier regions BK_SA and the word line driver regions BK_SWD, as well as technology for reducing the area of the memory array, is an important issue.
Recently, vertical MOS transistors, such as pillar-shaped transistors, have been developed. Because of the development of such vertical MOS transistors, the area required for transistors can be greatly reduced. Therefore, the area of memory cells and the area of a memory array can also be remarkably reduced. As a result, a reduction in the area of the sense amplifier regions BK_SA and the word line driver regions BK_SWD has also become an important issue.
FIG. 2 is a layout diagram showing the arrangement of circuits in a conventional semiconductor memory device. In FIG. 2, for clarity of understanding, sense amplifier regions, word line driver regions and junction regions are exaggerated in size relative to actual sizes thereof. Referring to FIG. 2, in each sense amplifier region BK_SA, bit line sense amplifiers BLSAs are arranged for sensing and amplifying data on a bit line BL. In each word line driver region BK_SWD, sub-word line drivers SWDs for driving word lines WL are arranged.
Further, in each junction region JNC, decoding drivers PXD<i> (i=0 to 3), designated as “PX drivers”, are arranged. Further, the entire wiring required to transmit pre-decoding signals PX<i> (i=0 to 3) to the decoding drivers PXD<i> is arranged to pass through the sense amplifier regions BK_SA. Further, the wiring required to transmit delayed decoding signals PX<i>D and inverted decoding signals PX<i>B, provided by the decoding drivers PXD<i>, is arranged to pass through the word line driver regions BK_SWD.
Further, in the junction region JNC of FIG. 2, first and second equalization drivers EQL_DR and EQR_DR, a pull-up voltage driver LAD, a pull-down voltage driver LABD, etc., are arranged. The first and second equalization drivers EQL_DR and EQR_DR generate first and second equalization signals EQL and EQR, respectively, for equalizing left and right bit lines BL connected to a corresponding bit line sense amplifier BLSA. The pull-up voltage driver LAD and the pull-down voltage driver LABD generate a pull-up driving signal LA and a pull-down driving signal LAB, respectively, for driving the pull-up sensing and pull-down sensing of the bit line sense amplifier BLSA.
Further, the entire wiring required to transmit the first and second equalization signals EQL and EQR, the pull-up driving signal LA, and the pull-down driving signal LAB, is arranged to pass through the sense amplifier regions BK_SA. In addition, the wiring required to transmit first and second connection control signals ISOR and ISOL for driving the bit line sense amplifiers BLSA, and a column select signal CSL is arranged to pass through the sense amplifier regions BK_SA.
Further, the wiring required to transmit power, such as a supply voltage VCC, a ground voltage VSS and a boosted voltage VPP, is arranged to pass through the sense amplifier regions BK_SA and the word line driver regions BK_SWD.
In this case, if transistors constituting the bit line sense amplifiers BLSA and the sub-word line drivers SWD are implemented using vertical MOS transistors, the area required for such transistors can be remarkably reduced. Therefore, the area required to implement the bit line sense amplifiers BLSA and the sub-word line drivers SWD is remarkably reduced (as shown in the parts of FIG. 3 indicated by oblique lines).
However, in the conventional semiconductor memory device, since the wiring required to transmit signals and/or voltages is arranged to pass through the sense amplifier regions BK_SA and the word line driver regions BK_SWD, possible reduction in the widths of the sense amplifier region BK_SA and the word line driver region BK_SWD (refer to w1 and w2 of FIGS. 2 and 3) is greatly restricted.
In particular, since the decoding drivers PXD<i> (i=0 to 3) are arranged in the junction region JNC, the wiring required to transmit a large number of pre-decoding signals PX<i> (i=0 to 3) and the wiring required to transmit the delayed decoding signals PX<i>D (i=0 to 3) and the inverted decoding signals PX<i>B (i=0 to 3) are arranged to pass through the sense amplifier regions BK_SA and the word line driver regions BK_SWD. Accordingly, it is very difficult to reduce the widths of the sense amplifier regions BK_SA and the word line driver regions BK_SWD.